Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology
Author(s) : AMITOJ SINGH, ANU GUPTA, SACHIN MAHESHWARI
Abstract
The Logical Effort model is mainly to reduce delay in a circuit, but does not show how to minimize powerandarea. This paper deals with an empirical modeling anddesign of logical effort for estimating powerin CMOS logic gates.Thepower is estimatedin a circuit using the power of standard inverter and the relationship established between Power(P)and Logical Effort(g), ElectricalEffort(h) and Parasitic (p) havebeen proposed in this paper.
No fo Author(s) : 3
Page(s) : 39 - 43
Electronic ISSN : 2278 - 215x
Volume 2 :
Issue 2
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