Journals Proceedings

Abstract

A new Cache memory cell has been proposed using the DCI logic gate. The principle and operation of the cell has been given. The current equation at each stage of the memory cell has been deduced. The dynamic response of the cell has been obtained by computer-simulation. The performance of our Cache memory cell has been compared with that of the IBM Cache memory cell. The cycle and access time of the proposed cell are 250ps and 210ps respectively, compared to earlier Cache memory cycle and access times, 1000ps and 650ps, respectively. Our Cache memory cycle time and access time can be further reduced since it is based on the DCI logic, which does not have much restriction on its size.