International Journal of Advances in Electronics Engineering
Author(s) : P.K GHOSH, GAURAV DHIMAN, MANOJ KUMAR, SATYAJIT ANAND
CMOS logic gates are basic building blocks for VLSI adder\'s circuits. The delay through these gates is related to their sizes and terminal loads. Logical effort is a technique, which gives insight about proper sizing of CMOS logic gates to have the minimum achievable delay. In this paper, we discuss first the technique of logical effort; three common architectures for VLSI adders are sized using logical effort to get the minimum possible delay. Simulated results are used to design fast CMOS circuits. A comparison between delays for these structures is presented according to simulation results in 32 nm standard CMOS process.