High throughput-less area efficient fpga implementation of block cipher aes algorithm
Author(s) : D.MAHESH KUMAR, M.SIRIN KUMARI, Y.RAMA DEVI
Abstract
This paper addresses design, hardware implementation and performance testing of AES algorithm. An optimized code for the Rijndael algorithm with 128-bit keys has been developed. The area and throughput are carefully trading off to make it suitable for wireless military communication and mobile telephony where emphasis is on the speed as well as on area of implementation.
No fo Author(s) : 3
Page(s) : 210 - 215
Electronic ISSN : 2250 - 3765
Volume 1 :
Issue 1
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