Journals Proceedings

International Journal of Advances in Computer Networks and Its Security

A Novel Transceiver Architecture for High- Speed Parallel Ethernet Network



The Ethernet network is currently used as the common way to transfer data between devices. As with all transceiver systems the transmission speed is the most critical factor. For high-resolution digitised images, for example, such network connections are often a bottleneck. The main objective of this paper is to create a full transceiver device as part of an embedded system, at both source and host devices that provide a high transmission speed. The main idea is to design a new system architecture, called Novel Reference Module (NRM), for both transmitter and receiver, based on four parallel Ethernet (PE) networks placed at the bottom of the system architecture, that connect to the devices at the opposite side. The four Ethernet ports connect to each other across the network media using a point-to-point network topology. Due to the high bandwidth it is not possible to use embedded processors to optimise the bandwidth for all network ports simultaneously. To this end we have developed a dedicated controller that controls the data flow and maximising the use of bandwidth. The Parallel Ethernet system builds as a software using Qsys builder, which is provided in Quartus II software from Altera, and tested using the SignalTap Analyzer tool, which is also provided by Altera. With this tool we demonstrate our embedded system using a StratixIV GX on DE4 board, which is provided by Terasic.

No fo Author(s) : 2
Page(s) : 17 - 21
Electronic ISSN : 2250 - 3757
Volume 6 : Issue 2
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