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International Journal of Advances in Computer Science and Its Applications

Predictable CPU Architecture Designed for Small Real-Time Applications – Implementation Results



The purpose of this paper is to describe and present the implementation results of nMPRA-MT processor concept designed for small real-time applications. Our target is to validate a fine-grained multithreading CPU architecture that uses replication and remapping techniques for the program counter, general purpose registers and pipeline registers. The new predictable CPU implementation is based on a hardware scheduler engine, being able to schedule dynamically a set of tasks on the five-stage pipeline assembly line. Using a FPGA device from Xilinx, we validate the innovative nMPRA-MT processor, interleaving different types of threads into the pipeline assembly line, providing predictability and hardware-based isolation for hard real-time threads. Mechanisms for synchronization and inter-task communication are also taken into consideration.

No fo Author(s) : 2
Page(s) : 141 - 148
Electronic ISSN : 2250 - 3765
Volume 6 : Issue 1
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