Journals Proceedings

Abstract

This paper presents the design and implementation of a high speed 32-tap finite impulse response (FIR) filter that employs the Distributive Arithmetic (DA) technique for the complex computation of Audio Coefficients and Multipliers. Distributive Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT), base structure of Field Programmable Gate Array (FPGA). Distributive Arithmetic algorithm (DA-FIR) technique is employed for reducing the complex computations, thereby increasing the speed and it also reduces the area and power consumption. The design is modeled using Verilog HDL and implemented on Virtex II Pro FPGA that consumes 39% resources of FPGA and shows the clock latency of 34 cycles at 192.45 MHz clock frequency.