Journals Proceedings

Abstract

Due to ever rising growth of wireless communication systems, the need for low power and cost effective devices is growing exponentially. The Phase locked loops (PLL) are the fundamental circuit elements of data transmission systems and have wide applications in data modulation, demodulation and mobile communication. Voltage control oscillators (VCO) are the critical and necessary building blocks of these PLL systems. In This paper the design and analysis of digital phase locked loop (DPLL) has been discussed. Phase locked-loops (PLLs) are widely using to generate well-timed on-chip clocks to be used in high-performance digital systems. The design is applied to the T-SPICE simulation program; implemented in a 1.2µm CMOS technology and at 5V supply voltage to operate VCO at a frequency of 987.6 KHz with a delay time of 202.49965ns.