Journals Proceedings

Abstract

Our life is filled by various modern electronic products. Semiconductor memories are essential parts of these products and have been growing in performance and density in accordance with Moore’s law like all silicon technology. The process technology has been scaling down from last two decades and to get the functional and high yielding design beyond 100-nm feature sizes the existing design approach needs to be modified to deal with the increased process variation interconnects processing difficulties, and other newly physical effects. Considerable increase in gate direct tunneling current in the nano-CMOS regime is because of scaling of gate oxide. Subthreshold leakage and gate direct tunneling current are no longer second-order effects. The effect of gate-induced drain leakage (GIDL) is easily visible designs, such as DRAM and low-power SRAM. All these effects cannot be ignored as it will lead to nonfunctional SRAM, DRAM, or any other circuit. Reducing the supply voltage which is now not a feasible solution in respect to stability of the SRAMs and on reducing the supply voltage the stability also disturbs. Power management is also a challenge in mobile applications. In this paper we have used leakage reduction technique to reduce the leakage power which reduces the leakage power from 40% to 50% for the SRAM cell at 45nm technology.