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International Journal of Advances in Electronics Engineering

Analysis and Simulation of a Low-Leakage 10T SRAM Bit-Cell using Dual-VthScheme at Deep Sub- Micron CMOS Technology

Author(s) : MANISHA PATTANAIK, NEERAJ KR. SHUKLA, R.K.SINGH, S.BIRLA, SVEEN NAGPAL

Abstract

Exponential growth of battery powered portable applications demanding new SRAM cell topologies with low-leakage. In this work, an analysis and simulation on P-P-N based 10T SRAM cell using dual-Vth scheme (at deep sub-micron technology) is presented. This work achieved stand-by leakage reduced by 74% and 77% at VDD=0.8V and VDD=0.7V respectively without losing cells performance at an area power trade-off. The simulation is being performed at 45nm CMOS technology, Vthn=0.22V, Vthp=0.224V, VDD=0.7 and 0.8V, and at T=270C.

No fo Author(s) : 5
Page(s) : 31 – 40
Electronic ISSN : 2278 - 215x
Volume 2 : Issue 3
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