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International Journal of Advancements in Electronics and Electrical Engineering

Preliminaries on a Hardware-Based Approach to Support Mixed-Critical Workload Execution in Multicore Processors



The use of multicore processors in general-purpose real-time embedded systems has experienced a huge increase in the recent years. Unfortunately, critical applications are not benefiting from this type of processors as one could expect. The major obstacle is that we may not predict and provide any guarantee on real-time properties of software running on such platforms. The shared memory bus is among the most critical resources, which severely degrades the timing predictability of multicore software due to the access contention between cores. To counteract this problem, we present in this paper a new approach that supports mixed-criticality workload execution in a multicore processor-based embedded system. It allows any number of cores to run less-critical tasks concurrently with the critical core, which is running the critical task. The approach is based on the use of a dedicated Deadline Enforcement Checker (DEC) implemented in hardware, which allows the execution of any number of cores (running less-critical workloads) concurrently with the critical core (executing the critical workload). This approach allows the exploitation of the maximum performance offered by a multiprocessing system while guaranteeing critical task schedulability. A case-study based on a dual-core version of the LEON3 processor was implemented and mapped in a Xilinx Spartan 3E FPGA.

No fo Author(s) : 2
Page(s) : 142 - 146
Electronic ISSN : 2319 - 7498
Volume 4 : Issue 2
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