Improved High Speed, Low Power CMOS Multiplier
Author(s) : ALAA HUSSEIN , AMEEN BIN OBADI
Abstract
A high speed four quadrant current mode multiplier is presented. It is based on CMOS devices arranged in dual trans-linear loops and working in saturation region. The designed circuit operates under the voltage supply of ±1.5V. Design simulation was carried out using Tanner EDA Tools v13.0 with level 49 parameters (BSIM3 v3.1) in 0.35μm standard CMOS technology. Simulation results show that the multiplier has a 3dB bandwidth of 440MHz, linearity error of 1.1% and maximum power consumption of 158μW. The analog multiplier is used to carry out amplitude modulation whose results are also reported.
No fo Author(s) : 2
Page(s) : 44 - 48
Electronic ISSN : 2319 - 7498
Volume 4 :
Issue 2
Full Paper PDF
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