International Journal of Advancements in Electronics and Electrical Engineering
Author(s) : ALAA HUSSEIN , AMEEN BIN OBADI
A high speed four quadrant current mode multiplier is presented. It is based on CMOS devices arranged in dual trans-linear loops and working in saturation region. The designed circuit operates under the voltage supply of ±1.5V. Design simulation was carried out using Tanner EDA Tools v13.0 with level 49 parameters (BSIM3 v3.1) in 0.35μm standard CMOS technology. Simulation results show that the multiplier has a 3dB bandwidth of 440MHz, linearity error of 1.1% and maximum power consumption of 158μW. The analog multiplier is used to carry out amplitude modulation whose results are also reported.