Journals Proceedings

Abstract

In recent years, low power design has become one of the main focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, where efforts are taken to reduce subthreshold leakage, operation of digital circuits in the subthreshold region utilizes this current to minimize power consumption in low-frequency systems. This research paper proposes novel design of 8-transistor latch. The design performance is evaluated by comparing it with the conventional design of the latch. The simulation results are analyzed at 65nm and 45nm technology to show the technology independence of the design. The proposed design of latch is better suitable for the low power VLSI applications.