A Low-Power Sample-and-Hold Amplifier using 0.05- μm CMOS Technology
Author(s) : HIMANSHU PUNDIR, RITURAJ SINGH RATHORE, VINOD KUMAR
Abstract
This paper presents a sample-and-hold circuit based on a cascode-miller compensation technique, utilizing a class-AB operational amplifier as an output stage. Also using the techniques of pre-charging and output capacitor coupling can mitigate the requirements for the op-amp, resulting in low power dissipation. Power consumption is about 300μW from a single 1- V power supply. The performance of this SHA is not degraded even if input frequency approaching up to Nyquist frequency.
No fo Author(s) : 3
Page(s) : 39 - 42
Electronic ISSN : 2319 - 7498
Volume 3 :
Issue 1
Full Paper PDF
Views : 649 | Download(s) : 209
