Journals Proceedings

Abstract

This paper presents an efficient FPGA-based architecture of CFAR target detector for radar system based on the automatic censored cell averaging (ACCA) detector based on ordered data variability (ODV). The ACCA–ODV detector estimates the unknown background level by dynamically selecting a suitable set of ranked cells and applying successive hypothesis tests. The proposed detector does not require any prior information about the non homogenous background environment. It uses the variability index statistic as a shape parameter to accept or reject the ordered cells under investigation. The detection process is achieved on the fly in realtime where the processing time must be lower than 0.5 μs for high resolution detection. The proposed architecture is based on the embedded software solution which consists on execution an the ANSI-C code of the detector over the Nios-II soft-core processor downloaded in the FPGA with the requires hardware components, such as on-chip memories, UART and JTAG interfaces and Avalon interfaces, to build the system on chip. Using the proposed approach for our embedded target detection system, the total delay is close to 0.38 μs for the ACCA-ODV algorithm, which satisfy the real-time constraints of 0.5 μs.