Journals Proceedings

Abstract

Design and implementation of a Data Acquisition System (DAS) in Field Programmable Gate Arrays (FPGA).Data is coming with a very fast rate from a single channel pipeline 12-bit, 500-MSPS analog to-Digital converter (ADS5463), which provides LVDS compatible output, module will accept data From ADC on every positive edge of the clock cycle and generate the control signal to highly Optimized CORESDR (Soft IP module), CORESDR generate all the signal required for external SDRAM module like CS#, RAS#, CAS#, WE# CKE and other control signal require for SDRAM. This project provides automatic address incrementing facility and configuration register, that can be Configured at a run time for different speed grade, write and read burst size. In this project, we are Using three such main module and main module controller on a single FPGA chip so that one can Able to transfer data into SDRAM with a very fast rate more than 100 mhz for infinitely long time With 100% reliability without loss of single word, and read data with a slower speed and transfer data Into DSP for further analysis. A tool used for this project “Actel Libero project manager” for programming, synthesizing, Place and route and timing analysis. It smart design takes care about whole programming flow.FPGA used: proasic3 A3P400