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Abstract

SRAM cell read stability and write-ability are major concerns in CMOS technologies, due to the progressive increase in VDD and transistor scaling. In this paper, we studied and comparedthe performance of 7TN (with NMOS access transistor), 7TP (with PMOS access transistor) andconventional 6T structure.SRAM cells have been simulated in SPICE with 0.35 ?m technology. The techniques that provide the highest data stability, the lowest power consumption, and the smalllayout area are identified. Both 7TN and 7TP cell provides higher write stability as compare to 6T SRAM cell (around 24% increase in SWM). Voltage swing of 7T is large than 6T. 7TN SRAM shows 51% power reduction and 7TP cell shows 62% ( write and read \'1\') power saving as compare to conventional 6T.