Journals Proceedings

International Journal of Advances in Electronics Engineering

A Comparative Study of Dynamic Latch Comparator



This paper presents the comparison between CMOS dynamic latch comparators. The circuit has been simulated using SPICE tool with 0.35?m technology, supply voltage of 3 V and 3.3V respectively. The circuits studied and simulated in this paper are Preamplifier dynamic latch circuit that consists of a preamplifier followed by a doubleregenerative dynamic latch and the Buffered dynamic latch circuit that consists of a basic dynamic latch comparator followed by an inverter buffer stage. The power dissipation of preamplifier latch and buffered latch comparator operating at frequency 160 MHz and 100 MHz are 960.129 ?W and 1.132 mW respectively.

No fo Author(s) : 2
Page(s) : 313 - 317
Electronic ISSN : 2278 - 215x
Volume 1 : Issue 1
Views : 634   |   Download(s) : 132