Journals Proceedings

Abstract

The Universal Serial Bus (USB2.0) is support data exchange between a host computer and a wide range of simultaneously accessible peripheral like Mouse, keyboard, Digital camera, Printer, scanner etc..The USB2.0 supported three types of data transmission rates, those are operated Low speed (1.5MHZ), High speed (12MHZ) & Full speed (480MHZ). In this paper our coverage is up to implementation of USB 2.0 Receiver protocol on FPGA kit [SPARTAN-II XC2S200]. The FPGA design of USB 2.0 Receiver protocol provides an interface for \'system on chip \'designer to connect UBS bus. This will save the design time and the time required for debugging and testing a USB controller. The USB 2.0 Receiver protocol has been developed in VHDL which is a widely used hardware description language and is supported by the major FPGA designer such as Xilinx and Altera. The VHDL code for the USB 2.0 Receiver protocol is synthesizable onto a Xilinx Spartan II FPGA and is synthesizable onto other types of FPGAs with minimal modification.