International Journal of Advances in Electronics Engineering
Author(s) : PRERNA PARDHY, S.S. LIMAYE, VIVEK KHETADE
The power dissipation of modern processors has been rapidly increasing along with increasing transistor count and clock frequencies. As clock frequency increases and feature size decreases, clock distribution and wire delays present a growing challenge to the designers of singly-clocked, globally synchronous systems. Power consumption is more in globally synchronous system due to the large global clock distribution network. To mitigate this problem we are suggesting Globally Asynchronous Locally Synchronous system for power reduction. GALS removes the need for global clock net and also provides efficient means for managing complexity and reuse of large architecture. Apart from power reduction, GALS has benefits such as multiple clock frequencies for IP blocks and dynamic frequency/voltage scaling, it supports concurrent data transfer, clock tree removal, IP core reusability. We are proposing a method that evaluates benefits of GALS together with clock gating to minimize power consumption. The result shows that power reduction upto 73% can be achieved with negligible area and performance overhead.